The structure of a Flash-type memory cell is generally similar to that of a conventional MOSFET transistor, except for the fact that the flash transistor has two gates instead of one. A top gate corresponds to the control gate of the transistor (as is the case for other MOS transistors), while another gate, the floating gate, is arranged between the control gate and the channel of the transistor. An inter-gate dielectric layer is arranged between the control gate and the floating gate, while a gate dielectric layer is arranged between the floating gate and the channel, so that the floating gate is fully insulated by these dielectric layers, and charges can be stored therein in a particularly durable manner.
The example of a NOR-type flash memory cell consisting of an NMOS transistor is described below. Such a cell is equivalent in its inactive state to a logic “1” because a current flows through the channel by applying an appropriate voltage to the control gate.
Such a memory cell can be programmed (to set it to the “0” logic state) by the following procedure that implements a hot electron injection phenomenon.
A very high voltage is applied to the control gate and to the drain. The channel is passing so that electrons flow from the source to the drain. The source-drain current is then sufficiently high for high-energy electrons (hot electrons resulting from the collision of the charges with the crystalline network of the channel) to reach the floating gate by passing through the gate dielectric layer.
These hot electrons are then trapped in the floating gate, which alters the threshold voltage of the transistor. This mechanism decreases the voltage in the floating gate, and increases the apparent threshold voltage of the transistor (so that a higher voltage must be applied to the control grate for the transistor to be able to be passing—ON state). However, in normal reading conditions, the coupling of the two gates is insufficient to render the transistor passing. The read current of a programmed memory cell is thus “0”.
The cell can be erased (reset to the “1” logic state) by applying a low voltage to the control gate so that the transistor is not passing (OFF state), and whether it contained a “0” or “1” (that is to say, whether it was programmed or not) is unimportant. A very high voltage is applied to the drain so that a high voltage, of opposite polarity to that implemented in programming, is thus applied between the control gate and the source. The electrical field between the two gates increases until electrons can escape from the floating gate through the gate dielectric layer by tunnel effect.
During this erasure operation, the floating gate voltage decreases and the apparent threshold voltage of the transistor decreases.
In order to read the cell, a nominal read voltage VDD is applied to the control gate. Depending on the status of the memory cell (programmed or erased), the transistor is either passing (ON state if it is erased) or blocked (OFF state if it is programmed).
A positive voltage is also applied to the drain (any value below VDD to avoid disturbances while obtaining an adequate read signal). The drain will then be discharged if the transistor is ON. An analysis amplifier can then read either the current or the voltage drop.
Such flash memory cells have the drawback that a very high voltage must be applied to the control gate during programming operations to generate the hot electrons capable of reaching the floating gate through the gate dielectric layer.
As it happens, such high programming voltages are undesirable in as much as they increase the complexity of the design of the peripheral circuits (dedicated circuitry implementing charge pumps is in particular necessary to generate these high voltages), they are likely to damage the cell and even disrupt the operation of nearby memory cells.
U.S. Pat. No. 5,455,791A describes a EEPROM device fabricated on a SOI substrate having a back semiconducting layer and a front semiconducting layer separated by a buried insulating layer. The EEPROM device comprises two separate control gates, a front control gate and a back control gate. The back control gate is formed by the back semiconducting layer and a back gate contact made of a conductive material that extends all over the back semiconducting layer and is separated from the buried insulating layer by the back semiconducting layer. The back control gate is not suitable to be used for performing a programming operation because of the distance separating the back gate contact from the channel region.
There is a need to resolve these problems of design complexity regarding the peripheral circuits and of reliability of the cell and of the circuit in general and that need is now satisfied by the present invention.